1. Technical Field
The invention relates generally to DRAM cells, and more specifically to a cell with enhanced SER immunity.
2. Background Art
A standard dynamic random access memory (DRAM) cell features a capacitor with one electrode coupled to ground potential and one electrode coupled to a source/drain electrode of a FET transfer device that has a gate electrode coupled to a word line and the other source/drain electrode coupled to a bit line. If the FET is an NFET, when the word line voltage rises the charge from the capacitor alters the voltage of the bit line sufficiently to be sensed by a differential amplifier.
One of the failure mechanisms for DRAM cells are errors due to extraneous charges that disrupt the charge stored on the capacitor. Such mechanisms are referred to as “soft errors,” because the radiation (such as alpha rays) that disrupts the charge stored on a capacitor does little to no physical damage. Typically such disruptions are dealt with by error correction codes (ECC), most commonly double error detect, single error correct (DED/SEC) Hamming codes that detect such bit storage errors and fix them on the fly. In fact some DRAMs are architected to include on-chip ECC circuitry so that the Hamming code methodology is carried out on on-chip. See for example U.S. Pat. No. 5,134,616, “Dynamic RAM with On-Chip ECC and Optimized Bit and Word Redundancy,” assigned to the assignee of the present invention.
However, in some applications ECC coding is not a practical solution to the problem of soft errors. One such application is embedded DRAM, in which an array of DRAM cells is embedded within a logic circuit. In such applications, the overhead costs associated with ECC are not economically justifiable; that is, the incremental cost of adding DRAM to a logic circuit becomes much more difficult to justify if ECC must be factored in.
One way of increasing soft error immunity without using ECC is to simply increase the size of the capacitance, e.g. using trench capacitors, stacked capacitors, or simply increasing the amount of chip surface area devoted to the capacitor. However, all of these solutions greatly increase the total area of the cell or drive increased process complexity, both of which increase manufacturing cost.
Another solution to reducing soft error rates (SER) is to utilize the so-called “differential” DRAM cell, in which two transistors are coupled to a common, floating capacitor. See U.S. Pat. No. 4,103,342, “Two-Device Memory Cell With Single Floating Capacitor,” assigned to the assignee of the present invention, and FR 2595160, “Coupled Memory Cell and Dynamic Memory Containing Such a Cell.”
In some art, the notions of trench or stacked capacitors have been combined with the differential DRAM cell concept to further reduce SER. See “High Density Memory Cell Structure With Two Access Transistors,” IBM Technical Disclosure Bulletin Vol. 31, No. 7, December 1988 pp. 409-417; U.S. Pat. No. 4,927,779, “Complementary Metal-Oxide-Semiconductor Transistor and One-Capacitor Dynamic-Random-Access Memory Cell and Fabrication Process Therefor;” U.S. Pat. No. 5,580,335, “Method of Forming a Buried-Sidewall-Strap Two Transistor One Capacitor Trench Cell.” Other art has combined the two device cell concept with stacked capacitors. See U.S. Pat. No. 5,606,189, “Dynamic RAM Trench Capacitor Device With Contact Strap.”
An FET technology that has received much recent attention is the so-called “FinFET” technology, in which a fin of silicon is defined on an SOI substrate, the fin having first and second lateral ends that are doped to form source/drain regions, and a central portion providing the FET channel. This central region is covered with polysilicon to form the gate electrode, and since gate electrode covers both major surfaces of the fin to form a “double gate” structure, the silicon body can be fully depleted of minority carriers to thus provide enhanced switching speeds. See e.g. “A Fully Depleted Lean-Channel Transistor (DELTA),” Hisamoto et al, International Electron Devices Meeting (IEDM)1989, paper 34.5.1, pg 833-36; and “Ultra-thin Body SOI MOSFET for Deep-sub-tenth Micron Era,” Choi et al, Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, IEDM 1999, Paper 3.7.1, pp. 919-21.
More recently, similar devices have been proposed as the transfer device for a single-capacitor DRAM cell. See U.S. Pat. No. 6,246,083, “Vertical Gain Cell and Array for a Dynamic Random Access Memory.”
While many of the foregoing teachings seek to address SER by increasing cell capacitance, the methods utilized to do so (greatly increasing cell area, and/or increasing the structural complexity of the capacitor) are suboptimal, particularly in applications such as embedded DRAM in which we seek to minimize the processing variances between the DRAM array and the surrounding logic. Therefore, a need has developed for a DRAM cell that has enhanced SER immunity and is of simple construction.